Imaging and video capabilities have become the trend in consumer electronics. Digital cameras, digital camcorders and video cellular phones are now common. Many other new gadgets are evolving in the market. These products require an efficient architecture with modules essential for video and image processing. These modules need to be connected in a modular way that is functionally flexible and efficient in silicon area, external memory bandwidth and design effort.
The prior art typically includes a digital signal processor (DSP) that provides the imaging and video capability. Imaging and video computation and data flow in the DSP poses multiple challenges of high data rate, heavy computation load and many variations of data flow. These video and imaging tasks require many processing stages. A typical system on chip (SOC) solution includes on-chip memory that is not large enough to hold each frame. The image is generally partitioned into blocks for movement among the processing stages. Sometimes each frame requires are multiple passes to an external memory, such as synchronous dynamic random access memory (SDRAM), due to algorithm dependency or hardware characteristics. Processing and traffic among multiple frames often overlap in a pipelined manner to increase processing throughput rate. This overlap complicates the data flow.